Recently, electronic devices such as, for example, mobile phones, portable computers, and personal digital assistants (PDAs), are reduced in size and weight, and have high functionality, and as a result, a semiconductor package to be mounted in an electronic apparatus requires a reduction in size and weight and high density packaging to a mount substrate. Under this circumstance, a wafer-level chip-size package (WLP-CSP), in which a bare chip is packaged in a wafer state, has been practically used. The WLP-CSP is a package having the same size as the bare chip, and is a wiring board that connects the bare chip to a printed circuit board (PCB). In this regard, a fan-out type WLP, in which a wiring layer is formed in a wide region exceeding a bare chip area, has begun to come into wide use.
The fan-out type WLP connects the bare chip and the PCB through a fine wiring, and the used wiring requires high functionality of a device, a minute size (high density of the line/space of about 3 μm or less), and high reliability. In addition, because it is also important to reduce the costs in the fan-out type WLP, Cu (copper) is used for fabricating a wiring, and a resin such as, for example, an epoxy-based resin or a phenol-based resin, is used for fabricating an insulating film.
Meanwhile, as a technology of mounting a semiconductor chip on a PCB with a fine wiring, there is a technology of mounting a plurality of semiconductor chips on the PCB through a single interposer board (a board only having a wiring layer). FIG. 1 illustrates an example of an interposer board 1. In FIG. 1, the interposer board 1 has a plurality of wiring layers 3 to 5 on a base board 2 by using a resin insulating film, and respective wiring layers are connected through vias 6. The wiring layer 3 is the first wiring layer from the base board 2, the wiring layer 4 is the second wiring layer from the base board 2, the wiring layer 5 is the first wiring layer from the base board 2, and the wiring layer 5 is called a rewiring layer.
A plurality of LSI chips 8 are mounted on the interposer board 1 through micro bumps 7. FIG. 1 illustrates only two LSI chips 8, but the number of LSI chips 8 on the interposer board 1 is not limited. In addition, the LSI chips 8 mounted on the interposer board 1 may transmit or receive signals to or from each other by the wiring layers 3 to 5 of the interposer board 1. Terminals 2T, which are connected to the wiring positioned in the first wiring layer 3, are disposed on the base board 2, and the terminals 2T are connected to land portions 10T formed on the PCB 10 through solder bumps 9.
The fine wiring in the fan-out type WLP or the interposer board is formed through a process generally called a semi-additive method, which includes patterning photoresist on seed layers made of Cu (copper), performing selective plating, and removing extra seed layers. The fine wiring will be described with reference to a structure of a portion of the interposer board 1, which is indicated by symbol A in FIG. 1, as an example.
FIG. 2A is a cross-sectional view illustrating an example of a Cu fine wiring 11 using a resin insulating film in a comparative technology. Three wiring layers 3, 4, and 5 formed using resin insulating films are positioned on a base board 2 made of a resin or Si (silicon). The Cu fine wiring 11 is positioned on a wiring layer 4, which is the second wiring layer from the base board 2, and an electrode 12, which is connected to the Cu fine wiring 11 through a via 6, is positioned on the wiring layer 5, which is the third wiring layer from the base board 2. In the comparative technology, the Cu fine wiring 11 is covered by the three resin insulating layers, so that the Cu fine wiring 11 does not come into contact with water or oxygen in the outside air, and as a result, oxidation of the Cu fine wiring 11 is prevented, and thus corrosion of the Cu fine wiring 11 is avoided.
FIG. 2B is a cross-sectional view illustrating a comparative technology in which a barrier film 13 is formed on the outer circumference of the Cu fine wiring 11 illustrated in FIG. 2A, and constituent elements, which are the same as those in FIG. 2A, will be denoted by the same symbols. As the barrier film 13, a SiN layer, a SiO2 layer, a SiON layer, an alumina layer, and the like may be used. In the comparative technology, the Cu fine wiring 11 does not come into contact with water or oxygen in the outside air by the barrier film 13 covering the outer circumferential portion of the Cu fine wiring 11, and as a result, oxidation of the Cu fine wiring 11 is prevented to avoid corrosion of the Cu fine wiring 11.
FIG. 2C is a cross-sectional view illustrating a comparative technology in which the Cu fine wiring 11 is formed on the first wiring layer 3 on the base board 2 by using a so-called damascene method used for a wiring in a silicon chip. Even in the case of the Cu fine wiring 11 formed on the first wiring layer 3 using the damascene method, a method of coating an upper portion of the Cu fine wiring 11 with a dense and inert film as the barrier film 13 is generally used. In a comparative technology illustrated in FIG. 2C, the second and third wiring layers 4 and 5 are formed at a remote side (outer side) of the barrier film 13 from the base board 2.
However, in the techniques for preventing oxidation of the Cu fine wiring in the comparative technologies as described above, the resin between the fine wiring 11 deteriorates by being oxidized or hydrolyzed by oxygen or water that diffuses and permeates from the environment, thereby affecting dielectric characteristics or the like. In addition, because water, oxygen, or the like permeates to the vicinity of the Cu fine wiring 11, the barrier film 13 itself deteriorates due to the influence of water, oxygen, or the like even though the Cu fine wiring 11 is covered by the barrier film 13, and as a result, the Cu fine wiring 11 is also corroded, and electrical conduction characteristics of the Cu fine wiring 11 are also adversely affected in some cases.
In a case where a dense inorganic film (SiN or SiO2, or Al2O3, etc.) is used as the barrier film 13 in the wiring structure itself using the resin insulating film, there is concern that a crack is formed due to a difference between the inorganic film and the resin in respect to a thermal expansion coefficient or stress. In order to avoid the crack, it is necessary to form the barrier film 13 to be very thin (at least 50 nm or less). Further, in order to form the very thin barrier film 13, a technique associated with a surface reaction, such as an atomic layer deposition (ALD) method, is generally and conveniently used.
However, when SiN, SiO2, Al2O3, or the like is used to form a very thin film as the barrier film 13 through the ALD method in a portion including the resin insulating film of the second wiring layer 4 and the Cu fine wiring 11 as illustrated in FIG. 2B, the following problems occur. That is, because of a difference in a reaction rate with an ALD source gas on the Cu or the resin, the barrier film 13 tends to be thinly deposited on the Cu, and thickly deposited on the resin, and there is a problem associated with reliability in that a probability that a crack is formed due to the thickly deposited barrier film 13 is high.
As a means for solving the problems, as illustrated in FIG. 2D, there is a structure in which an inorganic barrier film 14 is disposed in a portion which is located at a side distant from the base board 2 and is not in contact with the Cu fine wiring 11. This structure has an effect of preventing oxidation to a certain degree, but oxygen or the like in the environment, which has penetrated the resin insulating film, easily reaches the inorganic barrier film 14, and deteriorates the inorganic barrier film 14 itself so that the oxygen or the like reaches the Cu fine wiring 11. Therefore, this structure is also not sufficient to prevent the oxidation of the Cu fine wiring 11, that is, to improve the reliability of the Cu fine wiring 11. In particular, in the recent Cu fine wiring 11 having a line/space width of about 2 μm or less, the deterioration in electric resistance is very serious even if the Cu fine wiring 11 is slightly oxidized, and as a result, it is not effective even if the inorganic barrier film 14 is merely disposed in the portion that is located at a side distant from the base board and is not in contact with the Cu fine wiring 11.
The followings are reference documents.    [Document 1] Japanese Laid-Open Patent Publication No. 2006-135278 and    [Document 2] Japanese Laid-Open Patent Publication No. 2009-117560.